Background: the evolution of flash memory technology

NAND flash manufacturers have continually reduced the cost of each generation of flash memory, accelerating the adoption of flash storage. Each new generation of flash memory uses fewer electrons per cell to store data, and as a consequence, data integrity suffers and the expected life of the NAND is reduced. The transition from MLC (multi-level cell) to TLC (three-level cell) further exacerbates the problem because each cell must store more information. LSI® SHIELD™ technology uniquely combines adaptive code rates, smart handling of transient noise, and a multi-level error correction schema to deliver industry-leading error correction that helps transform the latest NAND flash memory into robust storage solutions.

 

SHIELD Error Correction

Features

  • Hard-decision LDPC (HLDPC)
  • DSP-aided soft-decision LDPC (SLDPC)
  • Parallel LDPC engines with specialized hardware assist
  • Adaptive code rate
  • Smart handling of noise
  • Multi-level error correction schema

LSI SHIELD technology is a unique implementation of low density parity-check (LDPC) code that combines hard-decision, soft-decision, and digital signal processing (DSP) to provide a comprehensive error correction solution for flash memory. Previous ECC techniques based mainly on Bose-Chaudhuri-Hocquenghem (BCH) codes strain to meet the broad spectrum of product requirements with newer flash. SHIELD technology innovations enable SSD manufacturers to deliver enterprise-class product life and data integrity, even using less expensive memory with higher error rates.

 

Adaptive Code Rate

The frequency of read errors varies across the blocks of any NAND flash memory chip. To deliver optimum reliability with minimal overhead, SHIELD technology implements a variable code rate per block that increases ECC for weak blocks and reduces ECC for strong blocks. The allocation of ECC space is dynamic, so the number of ECC bytes for a given block increases over time as a block ages and generates more errors. During the beginning of life (BOL) of the flash, the unused ECC space is automatically converted to additional over provisioning (OP) space. Then as the solid state drive (SSD) approaches its end of life (EOL), part of the OP is gradually consumed to enable a much stronger ECC.

 

SHIELD_diagram 

 

Smart Handling of Noise

Flash memory suffers from various types of noise including program/erase cycling, retention, and read disturb. Such noises may cause an HLDPC decode failure, triggering SLDPC and the associated performance penalty. The SHIELD error recovery policy includes a suite of techniques designed to identify transient noise sources, and to prevent additional failures within the same page, block or area of the chip.

 

Multi-level Error Correction Schema

SLDPC decoding using digital signal processing (DSP) techniques achieves better error correction than HLDPC decoding, but it triggers two types of latency associated with collection of additional channel information and decoding. To minimize the overall performance impact of error correction, SHIELD technology implements a multi-level retry schema that applies progressively stronger decoding methods. Multi-processor parallelism is utilized to further reduce latency.

 

SHIELD_diagram  

 

Proven LDPC Experience

LSI has extensive experience in LDPC error correction and coding, using the technology in TrueStore® hard disk drive read channels since 2010. This experience and engineering expertise is leveraged in the SHIELD error correction technology for SandForce® flash controllers. SHIELD technology will be available with LSI SandForce SF3700 family flash controllers.