Link Layer Processor - Offers a highly integrated solution for multiservice applications such as wireline access network and 2.5G/3G and 4G/LTE wireless access
- Optimizes applications for base stations and radio network controllers (BSC, RNC), packet transport networks, microwave backhaul, PON access networks, and access routers
- Supports a variety of wireless protocols, including Abis, TC/IMA, and HDLC/ML-PPP
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Product Banner
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Product Features / Benefits Features
- Up to the full payload of a synchronous optical network (SONET) OC-3/STM-1 frame
- Up to 16 LIU/bit serial interface ports
- Internal framer support for up to 16 DS1/J1/E1 links, including subrate HDLC processing
- Eight synchronous concentration highway interface (CHI) ports for direct TDM interface to time-slot interchanger (TSI) devices
- ATM/packet protocol mapping over Ethernet
- ATM protocol processing for TC/IMA
— Support for any combination of up to 84 IMA groups
or UNI links with fractional support
— From 1 to 32 links per IMA group
- ML/MC-PPP packet processing
- Multichannel high-level data link control (HDLC)
- PWE3 support for CESoPSN and SAToP with Buffer Adaptive, Differential, and Synchronous Clocking
- System interface block (SIB) that can connect to a data plane processor
- 8-bit SPI-3 (system packet interface Level 3), 8-bit/16-bit UTOPIA Level 2, or 8-bit/16-bit POS-PHY Level 2, multi-PHY slave system interface
Benefits
- Allows customers to easily migrate from traditional TDM networks to newer IP networks
- LLP's full bidirectional data bandwidth can be used entirely by a single protocol path or can be simultaneously partitioned among the three protocol paths, allowing migration from circuit switching (TDM) to cell switching (ATM) to packet switching (IP) on a common platform
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Product Brief (2)
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LLP Link Layer Processor Product Brief
LLP Link Layer Processor Product Brief
Version: Dec. 2008
Size: 2.94M
Language: English
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Nov 26, 2008 |
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Link Layer Processor (LLP V2.2) Product Brief
Version: 11-19-2008
Size: 2.94M
Language: English
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Nov 18, 2008 |
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Solution Brief (1)
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Pseudowire Emulation Edge to Edge
The LSI Link Layer Processor (LLP) system-on-a-chip supports Pseudowire Emulation Edge-to-Edge (PWE3) with multiple protocol and scaleable T1-E1 solutions. This PWE3 solution allows customers to use their current native service (TDM, Frame Relay, ATM, or Ethernet) over any packet-switched network.
Version: May 2009
Size: 122.2K
Language: English
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Jun 03, 2009 |
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White Paper (1)
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Multi-service convergence in wireless and wireline backhaul networks
Version: July 13, 2009
Size: 410.4K
Language: English
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Sep 24, 2009 |
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