Link Mapper

  • Integrates dual link layer processors and STS-3/12/STM-1/4 SONET/SDH mappers optimized for high density TDM applications in a single package
  • Applicable for RNC, Media Gateways, uWave, Packet Transport, and PON Access networks
Link MapperEnlarge this
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Features

  • Supports SONET/SDH 155.52 Mbits/s interface solutions for dual channelized OC-3/STM-1 support. May alternatively be used for partial termination of single/dual OC-12/STM-4. Full SONET/SDH compliant alarm reporting, overhead monitoring, and generation
  • Dedicated ports for the termination of up to six DS3/E3/STS-1 clear channel signals
  • Virtual tributary mapping supporting asynchronous, bit synchronous, and byte synchronous modes. M13/E13 mapping is also supported
  • DS1/J1/E1 framers support a variety of framing modes. Full alarm reporting, performance monitoring, as well as subrate HDLC capability
  • Flexible STS-1/DS3/E3/DS1/E1 cross connects
  • 8-bit SPI-3 (system packet interface level 3), 8-bit/16-bit UTOPIA Level 2, or 8-bit/16-bit POSPHY™ Level 2 multi-PHY slave system interfaces
  • Fractional DS1/J1/E1 logical channel mapping to each of the three protocol processing paths
  • ATM protocol processing for TC/IMA:
      —168 DS1/J1 links or 126 E1 links per slice, for up to
         168 IMA groups
  • AAL1 SAR processing:
      —Up to 1344 virtual circuits (VCs) with support for 
         structured data transfer (SDT) and unstructured data
         transfer (UDT) modes
  • HDLC processing:
      —HDLC framing and deframing for up to 1344 HDLC 
         channels (transmit and receive) with simultaneous
         processing for various packet types
  • PPP and ML/MC/PPP
  • PWE3 support for CESoPSN and SAToP with Buffer Adaptive, Differential, and Synchronous Clocking

Benefits

  • Allows customers to easily migrate from traditional TDM networks to newer IP networks
  • Flexible and programmable architecture
  • High density multiprotocol support in a single device
Product Brief (1)
White Paper (1)

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