SerDes Based SoCs
Prototyping Support for SerDes Based SoCs
Including an FPGA prototype phase as part of an SoC’s design and verification is popular for the many real-world system integration benefits. With gigabit serial protocols now commonplace, designers need to use accurate ASIC specific PHY’s in their prototypes to avoid the verification risks and compromises of adapting an FPGA serdes to verify an ASIC design.
GigaBlaze eval part is architected specifically with the needs of ASIC and SoC designers in mind. With 4 GigaBlaze transceivers, designers have access to industry leading ASIC SerDes IP to accurately prototype the functionality and electrical behavior of PCI Express, SAS, SATA, FibreChannel applications at rates up to 4.25Gbps.
To accelerate the time to develop a prototype get it up and running, LSI has teamed with Hardi Systems to develop a daughter card for their industry leading HAPS prototyping system. By solving high speed signal PCB layout and signal integrity issues in advance, Hardi’s daughter card removes the design and debug of a dedicated prototyping board from a projects verification critical path.
Features
- Industry leading 4.25 Gbps GigaBlaze ASIC transceivers
- "bond-out" style architecture ensures IP in bench-top prototypes has same logical and electrical behavior as in the final SoC
- 2 lanes dedicated for 2.5G PCI Express with standard PIPE interface
- 2 lanes configurable for serial storage and other protocol support: SAS, SATA, FibreChannel and more
- Double data rate (DDR) style interface for high bandwidth parallel FPGA connections
- Low pin count MDIO configuration interface
